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authorBorislav Petkov <bp@suse.de>2019-08-16 11:20:20 +0200
committerBorislav Petkov <bp@suse.de>2019-08-16 11:20:20 +0200
commitbaf98c148433daa620eae278486638fe945f4637 (patch)
treef3ac08b39c2b31f43c2d8578c0b57594bb14c572
parent10fa205d451a5f6c55bbc6fa26555445a442ceec (diff)
x86/speculation: Allow guests to use SSBD even if host does not
(bsc#1114279). suse-commit: 66db1d68a503531736cf09f70b760d7882a03a72
-rw-r--r--arch/x86/kernel/cpu/bugs.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index dc1ca14bfd24..3fbd6b11349b 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -1043,6 +1043,16 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
}
/*
+ * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper
+ * bit in the mask to allow guests to use the mitigation even in the
+ * case where the host does not enable it.
+ */
+ if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
+ static_cpu_has(X86_FEATURE_AMD_SSBD)) {
+ x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
+ }
+
+ /*
* We have three CPU feature flags that are in play here:
* - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
* - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
@@ -1059,7 +1069,6 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
x86_amd_ssb_disable();
} else {
x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
- x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
}
}