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authorPetr Tesarik <ptesarik@suse.cz>2019-07-19 22:19:02 +0200
committerPetr Tesarik <ptesarik@suse.cz>2019-07-19 22:44:47 +0200
commit0e7455b4e8f1d933b3f15e86798f7e607017b52c (patch)
tree1a570a7081369d8dee8d37cb875e8b8bd363785f
parent2d05d9387ef82b3ef0103ba6852a86ace4ac5d9d (diff)
s390/cpu_mf: add store cpu counter multiple instruction support
-rw-r--r--arch/s390/include/asm/cpu_mf-insn.h22
-rw-r--r--arch/s390/include/asm/cpu_mf.h17
2 files changed, 39 insertions, 0 deletions
diff --git a/arch/s390/include/asm/cpu_mf-insn.h b/arch/s390/include/asm/cpu_mf-insn.h
new file mode 100644
index 000000000000..a68b362e0964
--- /dev/null
+++ b/arch/s390/include/asm/cpu_mf-insn.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Support for CPU-MF instructions
+ *
+ * Copyright IBM Corp. 2019
+ * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
+ */
+#ifndef _ASM_S390_CPU_MF_INSN_H
+#define _ASM_S390_CPU_MF_INSN_H
+
+#ifdef __ASSEMBLY__
+
+/* Macro to generate the STCCTM instruction with a customized
+ * M3 field designating the counter set.
+ */
+.macro STCCTM r1 m3 db2
+ .insn rsy,0xeb0000000017,\r1,\m3 & 0xf,\db2
+.endm
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/s390/include/asm/cpu_mf.h b/arch/s390/include/asm/cpu_mf.h
index bc764a674594..81669852a5ce 100644
--- a/arch/s390/include/asm/cpu_mf.h
+++ b/arch/s390/include/asm/cpu_mf.h
@@ -15,6 +15,8 @@
#include <linux/errno.h>
#include <asm/facility.h>
+asm(".include \"asm/cpu_mf-insn.h\"\n");
+
#define CPU_MF_INT_SF_IAE (1 << 31) /* invalid entry address */
#define CPU_MF_INT_SF_ISE (1 << 30) /* incorrect SDBT entry */
#define CPU_MF_INT_SF_PRA (1 << 29) /* program request alert */
@@ -200,6 +202,21 @@ static inline int ecctr(u64 ctr, u64 *val)
return cc;
}
+/* Store CPU counter multiple for a particular counter set */
+static inline int stcctm(u8 set, u64 range, u64 *dest)
+{
+ int cc;
+
+ asm volatile (
+ " STCCTM %2,%3,%1\n"
+ " ipm %0\n"
+ " srl %0,28\n"
+ : "=d" (cc)
+ : "Q" (*dest), "d" (range), "i" (set)
+ : "cc", "memory");
+ return cc;
+}
+
/* Store CPU counter multiple for the MT utilization counter set */
static inline int stcctm5(u64 num, u64 *val)
{