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authorThomas Zimmermann <tzimmermann@suse.de>2019-01-10 15:58:59 +0100
committerThomas Zimmermann <tzimmermann@suse.de>2019-01-11 13:41:55 +0100
commitb47a5f2bef24bdc47c22b087ca4db30f4000afd2 (patch)
tree7528bfc75a2c3835ef3c9ee441a8d797ab792f63
parent5bd07024b863fce9754de990e3939f00ea4578d0 (diff)
drm/i915/psr: Remove wait_for_idle() for PSR2 (bsc#1113956)
-rw-r--r--drivers/gpu/drm/i915/intel_psr.c18
1 files changed, 7 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 4bd5768731ee..1891776cc1c4 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -721,8 +721,6 @@ int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- i915_reg_t reg;
- u32 mask;
if (!new_crtc_state->has_psr)
return 0;
@@ -737,21 +735,19 @@ int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
* not needed and will induce latencies in the atomic
* update path.
*/
- if (dev_priv->psr.psr2_enabled) {
- reg = EDP_PSR2_STATUS;
- mask = EDP_PSR2_STATUS_STATE_MASK;
- } else {
- reg = EDP_PSR_STATUS;
- mask = EDP_PSR_STATUS_STATE_MASK;
- }
+
+ /* FIXME: Update this for PSR2 if we need to wait for idle */
+ if (READ_ONCE(dev_priv->psr.psr2_enabled))
+ return 0;
/*
* Max time for PSR to idle = Inverse of the refresh rate +
* 6 ms of exit training time + 1.5 ms of aux channel
* handshake. 50 msec is defesive enough to cover everything.
*/
- return intel_wait_for_register(dev_priv, reg, mask,
- EDP_PSR_STATUS_STATE_IDLE, 50);
+ return __intel_wait_for_register(dev_priv, EDP_PSR_STATUS,
+ EDP_PSR_STATUS_STATE_MASK,
+ EDP_PSR_STATUS_STATE_IDLE, 50);
}
static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)