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authorTakashi Iwai <tiwai@suse.de>2018-08-03 14:03:49 +0200
committerTakashi Iwai <tiwai@suse.de>2018-08-03 14:04:09 +0200
commit7d89bb0765283f838bf156116d5b39f2f16e6287 (patch)
treed27ccfd90ce1565721bce84ce5c5213a1e096327
parent198e18d9b5829bc20c33b70a6ae35f137917eab0 (diff)
ASoC: topology: Add missing clock gating parameter when parsing
hw_configs (bsc#1051510). suse-commit: 7b51810d04083cfa66e8b7c24ede39cbb394f14f
-rw-r--r--include/uapi/sound/asoc.h7
-rw-r--r--sound/soc/soc-topology.c7
2 files changed, 13 insertions, 1 deletions
diff --git a/include/uapi/sound/asoc.h b/include/uapi/sound/asoc.h
index 62416a7c3b1a..ffc0ab625efc 100644
--- a/include/uapi/sound/asoc.h
+++ b/include/uapi/sound/asoc.h
@@ -130,6 +130,11 @@
#define SND_SOC_TPLG_DAI_FLGBIT_SYMMETRIC_CHANNELS (1 << 1)
#define SND_SOC_TPLG_DAI_FLGBIT_SYMMETRIC_SAMPLEBITS (1 << 2)
+/* DAI clock gating */
+#define SND_SOC_TPLG_DAI_CLK_GATE_UNDEFINED 0
+#define SND_SOC_TPLG_DAI_CLK_GATE_GATED 1
+#define SND_SOC_TPLG_DAI_CLK_GATE_CONT 2
+
/* DAI physical PCM data formats.
* Add new formats to the end of the list.
*/
@@ -315,7 +320,7 @@ struct snd_soc_tplg_hw_config {
__le32 size; /* in bytes of this structure */
__le32 id; /* unique ID - - used to match */
__le32 fmt; /* SND_SOC_DAI_FORMAT_ format value */
- __u8 clock_gated; /* 1 if clock can be gated to save power */
+ __u8 clock_gated; /* SND_SOC_TPLG_DAI_CLK_GATE_ value */
__u8 invert_bclk; /* 1 for inverted BCLK, 0 for normal */
__u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */
__u8 bclk_master; /* SND_SOC_TPLG_BCLK_ value */
diff --git a/sound/soc/soc-topology.c b/sound/soc/soc-topology.c
index 09b91c6df6ee..316df1f23abe 100644
--- a/sound/soc/soc-topology.c
+++ b/sound/soc/soc-topology.c
@@ -1979,6 +1979,13 @@ static void set_link_hw_format(struct snd_soc_dai_link *link,
link->dai_fmt = hw_config->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
+ /* clock gating */
+ if (hw_config->clock_gated == SND_SOC_TPLG_DAI_CLK_GATE_GATED)
+ link->dai_fmt |= SND_SOC_DAIFMT_GATED;
+ else if (hw_config->clock_gated ==
+ SND_SOC_TPLG_DAI_CLK_GATE_CONT)
+ link->dai_fmt |= SND_SOC_DAIFMT_CONT;
+
/* clock signal polarity */
invert_bclk = hw_config->invert_bclk;
invert_fsync = hw_config->invert_fsync;