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authorBen Dooks <ben-linux@org.rmk.(none)>2005-02-12 19:57:14 +0000
committerRussell King <rmk@flint.arm.linux.org.uk>2005-02-12 19:57:14 +0000
commit383f117f2d9e637af24ed61794ba66f377bd10a0 (patch)
tree24313a2678514e1d20dbf3f4bd760b1b83f5a900
parent4d436945cd2c8023947b545afda374cd91b6ac2c (diff)
[ARM PATCH] 2471/1: S3C2440 - fix S3C2440_CAMDIVN register address
Patch from Ben Dooks Off by 4 error on S3C2440_CAMDVIN register address, and re-indented the pll calculation code to proper C style. Thanks to Guillaume Gourat for spotting the register mistake Signed-off-by: Guillaume Gourat Signed-off-by: Ben Dooks Signed-off-by: Russell King
-rw-r--r--include/asm-arm/arch-s3c2410/regs-clock.h19
1 files changed, 10 insertions, 9 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index 0cc629fe1b29..a6281f464d81 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -15,6 +15,7 @@
* 19-06-2003 Ben Dooks Created file
* 12-03-2004 Ben Dooks Updated include protection
* 29-Sep-2004 Ben Dooks Fixed usage for assembly inclusion
+ * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat)
*/
#ifndef __ASM_ARM_REGS_CLOCK
@@ -77,17 +78,17 @@
static inline unsigned int
s3c2410_get_pll(int pllval, int baseclk)
{
- int mdiv, pdiv, sdiv;
+ int mdiv, pdiv, sdiv;
- mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
- pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
- sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
+ mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
+ pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
+ sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
- mdiv &= S3C2410_PLLCON_MDIVMASK;
- pdiv &= S3C2410_PLLCON_PDIVMASK;
- sdiv &= S3C2410_PLLCON_SDIVMASK;
+ mdiv &= S3C2410_PLLCON_MDIVMASK;
+ pdiv &= S3C2410_PLLCON_PDIVMASK;
+ sdiv &= S3C2410_PLLCON_SDIVMASK;
- return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv);
+ return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv);
}
#endif /* __ASSEMBLY__ */
@@ -95,7 +96,7 @@ s3c2410_get_pll(int pllval, int baseclk)
#ifdef CONFIG_CPU_S3C2440
/* extra registers */
-#define S3C2440_CAMDIVN S3C2410_CLKREG(0x14)
+#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18)
#define S3C2440_CLKCON_CAMERA (1<<19)
#define S3C2440_CLKCON_AC97 (1<<20)