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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2005-10-26 01:59:00 -0700
committerLinus Torvalds <torvalds@g5.osdl.org>2005-10-26 10:39:43 -0700
commit958d24df82e021704437da0789c47fcf581e4b85 (patch)
tree33b544fb4d5282123ec38705160d7a316e005b55
parent1c6fe9465941df04a1ad8f009bd6d95b20072a58 (diff)
[PATCH] ppc64: Fix wrong register mapping in mpic driver
The mpic interrupt controller driver (used on G5 and early pSeries among others) has a bug where it doesn't get the right virtual address for the timer registers. It causes the driver to poke at the MMIO space of whatever has been mapped just next to it (ouch !) when initializing and causes boot failures on some IBM machines. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
-rw-r--r--arch/ppc64/kernel/mpic.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/ppc64/kernel/mpic.c b/arch/ppc64/kernel/mpic.c
index cc262a05ddb4..5f5bc73754d9 100644
--- a/arch/ppc64/kernel/mpic.c
+++ b/arch/ppc64/kernel/mpic.c
@@ -506,8 +506,8 @@ struct mpic * __init mpic_alloc(unsigned long phys_addr,
mpic->senses_count = senses_count;
/* Map the global registers */
- mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000);
- mpic->tmregs = mpic->gregs + (MPIC_TIMER_BASE >> 2);
+ mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x2000);
+ mpic->tmregs = mpic->gregs + ((MPIC_TIMER_BASE - MPIC_GREG_BASE) >> 2);
BUG_ON(mpic->gregs == NULL);
/* Reset */