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authorWang Zhenyu <zhenyu.z.wang@intel.com>2007-04-25 15:07:38 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2007-05-01 17:06:03 -0700
commitab02a65798ea8b940ea5645655238c778d4e4765 (patch)
tree41073a207da6be35fff6055dcc8901dd529b7967
parent27797cc764b52d417f5daf5703d4fa9f98867185 (diff)
AGPGART: intel_agp: fix G965 GTT size detect
[AGPGART] intel_agp: fix G965 GTT size detect On G965, I810_PGETBL_CTL is a mmio offset, but we wrongly take it as pci config space offset in detecting GTT size. This one line patch fixs this. Signed-off-by: Wang Zhenyu <zhenyu.z.wang@intel.com> Signed-off-by: Dave Jones <davej@redhat.com> Cc: Chuck Ebbert <cebbert@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r--drivers/char/agp/intel-agp.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index 84787ce5f72a..ed1d380905c7 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -405,9 +405,8 @@ static void intel_i830_init_gtt_entries(void)
if (IS_I965) {
u32 pgetbl_ctl;
+ pgetbl_ctl = readl(intel_i830_private.registers+I810_PGETBL_CTL);
- pci_read_config_dword(agp_bridge->dev, I810_PGETBL_CTL,
- &pgetbl_ctl);
/* The 965 has a field telling us the size of the GTT,
* which may be larger than what is necessary to map the
* aperture.