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authorAlex Deucher <alexander.deucher@amd.com>2012-08-06 17:06:03 -0400
committerAlex Deucher <alexander.deucher@amd.com>2012-08-13 10:50:53 -0400
commitecd67955fd4c8e66e4df312098989d5fa7da624c (patch)
tree2520777f3f6a0d84b15c4d186555c80525636b23
parent81ee8fb6b52ec69eeed37fe7943446af1dccecc5 (diff)
drm/radeon: fix ordering in pll picking on dce4+
No functional change, but re-order the cases so they evaluate properly due to the way the DCE macros work. Noticed by kallisti5 on IRC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index dc279ebf7afb..c6fcb5b86a45 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1531,12 +1531,12 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
* crtc virtual pixel clock.
*/
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
- if (ASIC_IS_DCE5(rdev))
- return ATOM_DCPLL;
+ if (rdev->clock.dp_extclk)
+ return ATOM_PPLL_INVALID;
else if (ASIC_IS_DCE6(rdev))
return ATOM_PPLL0;
- else if (rdev->clock.dp_extclk)
- return ATOM_PPLL_INVALID;
+ else if (ASIC_IS_DCE5(rdev))
+ return ATOM_DCPLL;
}
}
}