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authorPaul Mackerras <paulus@ozlabs.org>2017-09-13 14:51:24 +1000
committerMichael Ellerman <mpe@ellerman.id.au>2017-09-15 08:41:18 +1000
commit1bc944cee663f232e3c37b15a6b2f9185bca413c (patch)
treeae728c691c85dbe244a163f02dc318e3871811c5
parentbac65d9d87b383471d8d29128319508d71b74180 (diff)
powerpc: Fix handling of alignment interrupt on dcbz instruction
This fixes the emulation of the dcbz instruction in the alignment interrupt handler. The error was that we were comparing just the instruction type field of op.type rather than the whole thing, and therefore the comparison "type != CACHEOP + DCBZ" was always true. Fixes: 31bfdb036f12 ("powerpc: Use instruction emulation infrastructure to handle alignment faults") Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Tested-by: Michal Sojka <sojkam1@fel.cvut.cz> Tested-by: Christian Zigotzky <chzigotzky@xenosoft.de> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
-rw-r--r--arch/powerpc/kernel/align.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
index 26b9994d27ee..43ef25156480 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c
@@ -341,7 +341,7 @@ int fix_alignment(struct pt_regs *regs)
type = op.type & INSTR_TYPE_MASK;
if (!OP_IS_LOAD_STORE(type)) {
- if (type != CACHEOP + DCBZ)
+ if (op.type != CACHEOP + DCBZ)
return -EINVAL;
PPC_WARN_ALIGNMENT(dcbz, regs);
r = emulate_dcbz(op.ea, regs);