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authorTakashi Iwai <tiwai@suse.de>2018-07-26 20:49:00 +0200
committerTakashi Iwai <tiwai@suse.de>2018-07-26 20:49:55 +0200
commit775b803849c280619c0fa59528198bb52858cf39 (patch)
tree77131b4b859855707f5473cb589ef82ada0723de
parent59a63769ef15f9c9ec8b2ba8da5cf78a3d05ff34 (diff)
clk: at91: PLL recalc_rate() now using cached MUL and DIV values
(bsc#1051510). suse-commit: 4b2acbbbb0ec506a31bd549c42f1f18bbb5fb0fd
-rw-r--r--drivers/clk/at91/clk-pll.c13
1 files changed, 1 insertions, 12 deletions
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
index 7d3223fc7161..72b6091eb7b9 100644
--- a/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@ -132,19 +132,8 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_pll *pll = to_clk_pll(hw);
- unsigned int pllr;
- u16 mul;
- u8 div;
-
- regmap_read(pll->regmap, PLL_REG(pll->id), &pllr);
-
- div = PLL_DIV(pllr);
- mul = PLL_MUL(pllr, pll->layout);
-
- if (!div || !mul)
- return 0;
- return (parent_rate / div) * (mul + 1);
+ return (parent_rate / pll->div) * (pll->mul + 1);
}
static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,